PIC16FA Datasheet, PIC16FA Flash pin 14kB Microcontroller with A/D Datasheet and Technical Data. PIC 16FA is a microcontroller manufactured by Microchip Inc. You can see its specifications and download the datasheet here. Microchip 16FA 8-bit Microcontrollers – MCU are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Microchip 16FA 8-bit.
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Ce document au format PDF 1. DSB Note the following details of the code protection feature on Microchip devices: All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets.
Most likely, the person doing so is engaged in theft of intellectual property. We at Microchip are committed to continuously improving the code protection features of our products. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue dqtasheet relief under that Act. Information contained dztasheet this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates.
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We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version datassheet this data sheet, please register at our Worldwide Web site at: The last character of the literature number is the version number, e. Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices.
The errata will specify the revision dahasheet silicon and revision of document to 61f876a it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: Customer Notification System Register on our Web site at www. The available features are summarized in Table The pinouts for these device families are listed in Table and Table The Reference Manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
Higher order bits are from the Status register.
Oscillator crystal input or external clock source input. External clock source input. Connects to crystal or resonator in Crystal Oscillator mode. ST Master Clear input or programming voltage output. Master Clear Reset input. This pin is an active low Reset to the device. Timer0 external clock input.
SPI slave select input. This buffer is a Schmitt Trigger input when used in Serial Programming mode. PORTB can be software programmed for internal weak pull-ups on all inputs. Daasheet single-supply ICSP programming enable pin. In-circuit debugger and ICSP programming clock. In-circuit debugger and ICSP programming data. Timer1 external clock input. Capture2 input, Compare2 output, PWM2 output. Capture1 input, Compare1 output, PWM1 output. PORTB can be software programmed for internal weak pull-up on all inputs.
Low-voltage ICSP programming enable pin. Parallel Slave Port data. Read control for Parallel Slave Port. Write control for Parallel Slave Port. Chip select control for Parallel Slave Port. These pins should be left unconnected. The program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. Accessing a location above the 16f786a implemented address will cause a wraparound.
The Reset vector is at h and the interrupt vector is at h. RP0 Bank 00 0 01 1 10 2 11 3 Each bank extends up to 7Fh bytes. The lower locations of each bank are reserved for the Special Function Registers.
All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access. Not a physical register. These registers are reserved; maintain these registers clear.
Adtasheet 18 Indirect addr.
These registers are implemented as static RAM. A list of these registers is given in Table Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section. The upper byte of the program counter is not directly accessible. These registers can be addressed from any bank. The Status register can be the destination for any instruction, as with any other register.
If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the Status register as destination may be different than intended. For other instructions not affecting any status bits, see Section The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction.
For borrow, the polarity is reversed. To achieve a 1: User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. RB4 pins changed state; a mismatch condition will continue to set the bit.
(PDF) 16F876A Datasheet download
Reading PORTB will end the mismatch condition and allow the bit to be cleared must be cleared in software. RB4 pins have changed state Legend: The PIE1 register contains the individual enable bits for the peripheral interrupts. The PIR1 register contains the individual flag bits for the peripheral interrupts. User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
The conditions that will set this bit are: Unused in this mode. BOR is unknown on Power-on Reset.
16FA Datasheet, PDF – Alldatasheet
It must be set by the user and checked on subsequent Resets datasyeet see if BOR is clear, indicating a brown-out has occurred. The low byte comes from the PCL register which is a readable and writable register. On any Reset, the upper 16f87a of the PC will be cleared. Figure shows the two situations 16f876q the loading of the PC.
When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. PCL 8 Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary each byte block.
The stack dataeheet is not part of either program or data space and the stack pointer is not readable or writable. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth daatasheet overwrites the second push and so on.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Writing to the INDF register indirectly results in a no operation although status bits may be affected.